Network processors are generally used for analyzing and processing packet data for routing and switching packets in a variety of applications, such as network surveillance, video transmission, protocol conversion, voice processing, and internet traffic routing. Early types of network processors were based on software-based approaches with general-purpose processors, either singly or in a multi-core implementation, but such software-based approaches are slow. Further, increasing the number of general-purpose processors had diminishing performance improvements, or might actually slow down overall network processor throughput. Newer designs add hardware accelerators in a system on chip (SoC) architecture to offload certain tasks from the general-purpose processors, such as encryption/decryption, packet data inspections, and the like. These newer network processor designs are traditionally implemented with either i) a non-pipelined SoC architecture or ii) a fixed pipeline SoC architecture.
In a typical non-pipelined SoC architecture, general-purpose processors are responsible for each action taken by acceleration functions. A non-pipelined SoC architecture provides great flexibility in that the general-purpose processors can make decisions on a dynamic, packet-by-packet basis, thus providing data packets only to the accelerators or other processors that are required to process each packet. However, significant software overhead is involved in those cases where multiple accelerator actions might occur in sequence.
In a typical fixed-pipeline SoC architecture, packet data flows through the general-purpose processors and/or accelerators in a fixed sequence regardless of whether a particular processor or accelerator is required to process a given packet. For example, in a fixed sequence, a single accelerator within the fixed pipeline cannot be employed without employing the entire fixed pipeline. This fixed sequence might add significant overhead to packet processing and has limited flexibility to handle new protocols, limiting the advantage provided by using the accelerators.
Network processors are generally used for analyzing and processing packet data for routing and switching packets in a variety of applications, such as network surveillance, video transmission, protocol conversion, voice processing, and internet traffic routing. A network processor might employ a destination Media Access Control (MAC) address embedded in a packet generated by a source network device to transmit the packet to one or more appropriate target devices.
A network processor operating in accordance with IEEE 802.1D (see sections 7.8 and 7.9 of 802.1D-2004, included by reference herein) might “learn” MAC addresses of source and destination network devices to provide more efficient processing of packets. To “learn” MAC addresses, a network processor might store a table of MAC addresses and the corresponding port to which the device having that MAC address is connected. When a packet is received from a new network device, the network processor stores the MAC address and the port from which the packet was received. Thus, when a received packet is destined for a MAC address that is stored in the table, the network processor forwards the packet to the port stored in the table without sending traffic on other ports. A network processor operating in accordance with IEEE 802.1D might also remove older or unused MAC addresses from the table (“aging”). MAC address aging maintains efficient processing of packets by removing infrequently used addresses from the table. Removing infrequently used addresses saves storage space and allows the network processor to find the MAC addresses more quickly.
Many hardware-based MAC address learning and aging mechanisms support higher-speed performance in part because they store MAC addresses in dedicated on-chip memory, typically limiting maximum usable table sizes. Many software-based MAC address learning and aging mechanisms support high table capacity using external DRAM, though they often have slower performance and consume a non-trivial amount of processing resources to maintain and check the address table.